1. Field of the Invention
The present invention relates to methods of using a developer-soluble protective layer under a carbon underlayer in a multilayer stack and the microelectronic structures thereof.
2. Description of Related Art
As the semiconductor industry continues to push the boundaries of lithographic techniques, methods to make successively smaller features have been developed. One of these methods is multilayer processing.
Multilayer processes are quickly becoming the standard process at critical pattern levels because they allow a thin imaging layer without significant loss of resolution or increase in feature roughness. A typical multilayer stack includes a planarizing carbon-rich layer (e.g., carbon hardmask, amorphous carbon, or spin-on carbon layer) on the substrate surface, a pattern transfer layer (e.g., hardmask or spin-on glass) adjacent the carbon-rich layer, and an imaging layer (e.g., photoresist) adjacent the pattern transfer layer (i.e., “on top of” the entire stack). An anti-reflective coating may sometimes be present underneath the imaging layer. Typical lithographic processes are used to form a pattern on the imaging layer, which is then etched down into the substrate. The alternating stack allows for selective etching between layers. The pattern is first transferred to the pattern transfer layer using a reactive-ion etch (RIE), typically with a fluorocarbon etch gas (e.g., CF4 or CHF3), along with O2 or other gases to tune the profile. This pattern is then transferred into the underlying carbon layer, typically in an oxygen-based etch, such as O2, O2/N2, CO, or CO2 depending on the desired level of anisotropy. These successive pattern transfers ensure enough mask thickness to etch deeply into the device layer, without as much critical dimension (CD) loss and roughness as would occur using only a single layer of relatively thicker or slower-etching bottom anti-reflective coating underneath the imaging layer. The drawbacks to multilayer processing are the added complexity and the need to control profile through multiple layers so that the etch bias of the pattern is not excessive. At the gate level, especially high-k/metal-gate integration (HKMG), some care must also be taken to avoid damaging the gate oxide. This limits some dry etch choices where oxidation of the high-k dielectric or other forms of plasma damage might occur. These successive etches can also have detrimental effects. Repeated etching can deteriorate the pattern from both loss of fidelity and changes in profiles due to the partial isotropic nature of RIE. Since multilayer processes are also used in gate level patterning, there is concern about stochastic damage. An example of this sort of stochastic damage is the oxidization of metal gates on the substrate by the etch gas.
A variety of etch processes have been developed and tuned to minimize the challenges listed above, but they still rely on etch tuning. If a process could be developed to allow the use of a broader range of gases, while protecting the substrate from etch damage, it would mitigate the challenges that multilayer processing schemes are currently facing with the multiple etches.
Part of the manufacturing of an integrated circuit chip is to dope the silicon substrate to change its electrical characteristics. This is typically performed by driving ions into the surface of the wafer (“ion implantation”), then heating the wafer to allow the new elements to become electrically active. A protective mask is usually formed using photolithography to ensure the ions are only implanted in the desired (open) areas, while blocking the ions from being implanted in other (covered) areas. Until recently, an anti-reflective coating and a photoresist layer were sufficient to shield the substrate from the ion implant step. However, as feature sizes shrink, photoresist layers have become thinner and thinner to achieve better resolution and control. This requires the introduction of additional layers, such as hardmasks, to the stack. Likewise, the ion implant step becomes more and more difficult, as the thickness of material necessary to shield the substrate from ions does not change, but the size of features and the spacing between them continues to shrink. This causes an increase in the aspect ratio of the features thus raising the aspect ratio of the photoresist, and necessitating new processing methods. In addition, as this aspect ratio increases, the stability of the structures decreases. This loss of stability can lead to line collapse, or other failures.
The implant process has faced two major challenges, namely, sensitive substrates and increasing aspect ratios. In some cases, the wafer has a layer of silicon oxide placed under the lithography stack to scatter the incoming ions. In some cases, such a scattering layer cannot be used. In these cases, the substrate is usually sensitive, and processes (mostly RIE) used to remove inorganic layers (e.g., anti-reflective coatings) in the stack will damage the substrate. Coatings that can be removed with alternative processes would help solve these problems.
However, even with anti-reflective coatings, the increase in aspect ratio makes removal of the coating from between the features more difficult. Many methods have been proposed to aid in removing this residue. One such method is to coat the patterned anti-reflective coating and photoresist with a second layer of developer-soluble material, and then develop all three layers away in a second cleaning step. In another method, an electric field is applied to the structure before or during the post exposure bake (PEB) to help create features with better sidewalls. However, the proposed solutions are complicated and require additional materials or complicated processing steps to achieve effective removal of anti-reflective coating material from small features.
Thus, there remains a need in the art for improved materials and processes of creating microelectronic structures.